The present invention relates to integrated circuits, and more particularly to reducing a lateral etch undercut.
In an integrated circuit fabrication process, a layer of material (e.g. a conductive layer, a dielectric, or a semiconductor layer) can be patterned by an isotropic etch. A masked isotropic etch may involve an undercut—the etchant may etch the layer laterally under the mask. The undercut can be undesirable. There is a need to impede or eliminate the undercut etching.